ci: workflow: add build & run#7
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Get core revision: Different core revisions require different hanlding. To have an option to get the revision and apply different logic add the possibility to read masked revision from GSNPSID register. Set PHY Low Power Clock Select: For the HS UTMI+ PHY interface uses 48MHz for Low speed devices, instead of 480 MHz. We need to configure this after port completed a reset. Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
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Note: Control transfers only Add initial usb host driver for Synopsys DWC2 with vendor quirks. Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
Add vendor quirks for nRF54LM20 PHY configuration for DWC2 in host mode. Given the PHY is powered from USB, the PHY needs to be configured and powered on before registers can be accessed or the SoC freezes on any register access. Signed-off-by: Josuah Demangeon <josuah.demangeon@nordicsemi.no>
Enable the DWC2 host controller, for now requiring external power to be provided to the VBUS pin, however usable. Signed-off-by: Josuah Demangeon <josuah.demangeon@nordicsemi.no>
Small refactoring and logic change for nrf vendor quirks. Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
Add a simple workflow to build and run uhc on self hosted runner. Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
Add a small test for uhc driver with control transfer scenarios. Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
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Add a small workflow that builds and runs the uhc test on the self-hosted runner with esp32s3 board.
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